Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

dc.contributor.author	Mirmotahari, Omid
dc.contributor.author	Berg, Yngvar
dc.date.accessioned	2016-06-10T13:15:30Z
dc.date.accessioned	2016-10-21T09:01:32Z
dc.date.available	2016-06-10T13:15:30Z
dc.date.available	2016-10-21T09:01:32Z
dc.date.issued	2015
dc.identifier.citation	Circuits and Systems 2015, 6(5):121-135	nb_NO
dc.identifier.issn	2153-1293
dc.identifier.uri	http://hdl.handle.net/11250/2416833
dc.description.abstract	In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.	nb_NO
dc.language.iso	eng	nb_NO
dc.rights	Navngivelse 3.0 Norge	*
dc.rights.uri	http://creativecommons.org/licenses/by/3.0/no/	*
dc.title	Reliability of High Speed Ultra Low Voltage Differential CMOS Logic	nb_NO
dc.type	Journal article	nb_NO
dc.type	Peer reviewed
dc.date.updated	2016-06-10T13:15:30Z
dc.identifier.doi	10.4236/cs.2015.65013
dc.identifier.cristin	1244200

Except where otherwise noted, this item's license is described as Navngivelse 3.0 Norge