Beyond CMOS: Ternary and mixed radix CNTFET circuit design, simulation and verification

Abstract

For three-valued or ternary computing to be an alternative for binary, new multiple valued logic (MVL) electronic design automation (EDA) tools are needed. In this article we present a novel MVL logic synthesis tool to generate binary, ternary and hybrid (mixed radix) circuits using carbon nanotube FETs (CNTFETs). The web-based open source EDA tool aids in design, simulation and verification aspects including a direct netlist export to HSPICE. We demonstrate a fundamental building block of a balanced ternary computer using the tool, a ternary D flip-flop. We show that mixed radix design can reduce transistor count.