A study of CNTFET implementations for ternary logic and data radix conversion
Abstract
Ternary logic theory and CNTFETs
The basic theory of ternary logic and CNTFETs are explored and explained, to set a theoretical context
and build a base for the rest of the thesis. For ternary logic, this includes radix economy, ternary
notations, ternary-valued logic functions, ternary algebra, and conversion overhead. For CNTFETs,
topics discussed are the architecture, voltage threshold and characteristics, nanotube chirality, bene_ts
over MOSFETs, and simulation models.
Ternary-valued CNTFET circuit design and logic synthesis
The methods used for transistor- and gate-level circuit design of ternary-valued CNTFET circuits
are described, utilized, optimized, and automated with a logic synthesizer for generating simulation
_les with a research paper accepted in the SIMS 2020 conference, which includes proposed full adder
circuits compared with simulation results.
Radix conversion of data between binary and ternary
Several methods of data radix conversion is discussed and explained. One method is implemented and
optimized using the logic synthesizer, with circuit simulation results in HSPICE. It is shown that data
radix conversion can be done at high speeds with a low transistor count and power consumption with
the CNTFET circuits generated by the proposed logic synthesizer tool, with the proposed gate-level
design.
Comparing binary-valued circuits with ternary-valued circuits for the purpose of basic arithmetic
Several ternary-valued full adder circuits are compared with binary-valued full adder circuits, including
synthesized circuits as well as circuits found in related works. These circuits are compared in terms of
transistor count, power consumption, and signal delay, while scaling for the digit ratio between binary
and ternary. Despite any bene_ts of ternary logic, a ternary-valued adding circuit could not be found
to outperform an equivalent binary-valued circuit for the purpose of basic arithmetic in terms of PDP
and transistor count, with the CNTFET circuits used in this thesis.