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dc.contributor.authorLi, Gang
dc.contributor.authorLi, Jian
dc.contributor.authorLi, Tingyu
dc.contributor.authorWang, Kaiying
dc.identifier.citationJournal of Power Sources. 2019, 425 39-43.en_US
dc.description.abstractWith the ever-increasing development of micro/nano electronic systems, the need grows for smart and efficient on-chip energy-storage devices with high-performance and long lifetime. In this work, for the first time we demonstrate TiO2 nanotube arrays (TNTAs) as a high-surface-area scaffold to construct 3D nanostructured electrode on planar silicon substrate for on-chip supercapacitors. The ordered TNTAs are grown by directly anodizing Ti film sputtered on planar silicon substrate. The TNTAs are then electrochemically reduced to enhance their electrical conductivity. The reduced TNTAs exhibit both extremely low series resistance of 5.7 Ω and optimal specific capacitance of 5.6 mF cm−2 at 0.05 mA cm−2, which is 5 times higher than that of pristine TNTAs on silicon substrate. Furthermore, the reduced TNTAs are used as scaffolds to support MnO2 nanoparticles by electrochemical deposition. The MnO2 decorated TNTAs show maximum specific capacitance 20.6 mF cm−2 (volumetric specific capacitance of 103 F cm−3) at 0.05 mA cm−2 as well as excellent cycling stability with 82.1% capacitance retained after 3000 charge-discharge cycles. Such integration of silicon based TNTAs might open up new opportunities to construct 3D nanostructured electrodes, free of expensive and complicated MEMS technologies, for high-performance on-chip supercapacitors.en_US
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internasjonal*
dc.titleTiO2 nanotube arrays on silicon substrate for on-chip supercapacitorsen_US
dc.typePeer revieweden_US
dc.typeJournal articleen_US
dc.source.journalJournal of Power Sourcesen_US

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Attribution-NonCommercial-NoDerivatives 4.0 Internasjonal
Except where otherwise noted, this item's license is described as Attribution-NonCommercial-NoDerivatives 4.0 Internasjonal