Exploring Ternary Computing: Design of a Superscalar CPU and Carry-Lookahead Adder

Abstract

This thesis explores the design and architecture of a balanced ternary RISC-V-like Energy efficient Balanced tErnary Logic (REBEL)-2 Central Processing Unit (CPU). There is a growing interest in ternary computing due to the potential performance and efficiency benefits. The development of this type of system has its own challenges and pitfalls due to the differences and complications that can arise from its use. It continues the MSc work of Erica Fegri [1] on ternary counter design and the PhD work of Steven Bos [2] on the REBEL-2 Instruction Set Architecture (ISA) and ternary CPU design.The research examines several important topics:• The current implementations of fast adder structures in balanced ternary logic• The implementation of a carry-lookahead adder for balanced ternary• The design of a balanced ternary CPU implementing the REBEL-2 ISA• The required additions to support a superscalar architecture, allowing for parallel out-of-order process execution with in-order completionThis research proposes a solution for a balanced ternary carry-lookahead adder and explains the method of finding the solution. It also proposes a CPU design that implements REBEL-2 and shows a general design for a superscalar implementation. Some key components that should be present in the superscalar design have been identified, and a path forward to further develop the design is presented.This research not only enhances the understanding of fast balanced ternary adders but also demonstrates its practical application. The implementation of the adder serves as a verification of the logic, showcasing the relevance of this research.