RV32I To REBEL (R2R): A ternary compiler pipeline for C programs

Abstract

With Moore’s Law nearing its end and Dennard Scaling having reached its end two decades ago, there is a growing interest in finding new ways to improve the efficiency of Integrated Circuits (ICs) and microarchitectures. Ternary, a potentially more efficient numbering system than binary, is in this thesis explored in relation to compiling existing C-coded software to ternary assembly code without having to modify the source code itself.

As part of the thesis, we propose a pipeline to compile C-coded programs to a ternary equivalent of the binary RISC-V RV32I Instruction Set Architecture (ISA). In cooperation with supervisor Steven Bos, and based on his ternary ISA and Central Processing Unit (CPU) design RISC-V-like Energy-efficient Balanced tErnary Logic (REBEL)-2, we propose a new REBEL ISA able to fully cover RV32I.

As part of the pipeline, we propose a software application to both translate RV32I assembly code to REBEL assembly code, and to generate simulation statistics from RV32I and REBEL assembly code.

To verify our pipeline, we propose a test framework capable of verifying correct translation and simulation of every RV32I instruction and their REBEL translations.

Finally, we propose a set of C-coded programs that we benchmark through our pipeline. We generate simulation statistics from the RV32I and REBEL representations of these programs, and discuss the simulation results. We conclude that ternary has a great overall potential, particularly for certain identified tasks.