Reliability of High Speed Ultra Low Voltage Differential CMOS Logic
Journal article, Peer reviewed
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http://hdl.handle.net/11250/2416833Utgivelsesdato
2015Metadata
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Sammendrag
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.